The present invention is directed generally to integrated circuits. More particularly, the invention provides a method and apparatus for leakage current testing for integrated circuit memory devices. Merely by way of example, the invention provides techniques for monitoring cell current in a memory device for detecting word line leakage cause by process defects. But it would be recognized that the invention has a much broader range of applicability. For example, the present invention can be applied for testing other leakage conditions in integrated circuit memory devices.
FIG. 1 is a block diagram illustrating a conventional memory device 100. As shown, memory device 100 includes a word line power generator 101 coupled to memory sectors 110, 111, . . . , 119, etc. During memory operation, word line power generator 101 maintains a voltage required by the word lines. For example, during a read operation, a read voltage level is required. As is known, leakage conditions often exist in a memory device. Conventionally, the leakage conditions are often determined by monitoring power consumption of the memory device. As discussed below, conventional techniques have various limitations, and an improved technique for memory leakage testing is desired.